1: A pulse in a certain waveform has a frequency of . It repeats itself every
a. 1 msec
b. 20 msec
c. 50 msec
d. None
2: In a certain digital waveform, the period is four times the pulse width. The duty cycle is
a. 25%
b. 50%
c. 75%
d. 100%
3: The weight of the 1 in the binary number 10000
a. 20
b. 22
c. 23
d. 24
4: Which odd parity code is in error
a. 1011
b. 1110
c. 0101
d. 1000
5: Which even parity code is in error
a. 1100011
b. 0010100
c. 1010101
d. 1111100
6: The decimal equivalent of 1000 is
a. 2
b. 4
c. 6
d. 8
7: The difference of 1000-100 equals
a. 100
b. 101
c. 110
d. 111
8: The decimal number is expressed in the s complement form as
a. 01111010
b. 10100010
c. 11011110
d. 01011101
9: A single-precision floating-point binary number has a total of
a. 8 bits
b. 16 bits
c. 24 bits
d. 32 bits
10: The octal number 25 has a binary equivalent
a. 001011
b. 010101
c. 110011
d. 100101
11: . . .. gate is used for conjunction operation
a. NOT
b. OR
c. AND
d. X-OR
12: An inverter performs an operation known as
a. Complementation
b. Assertion
c. Inversion
d. Both a and c
13: The output of an AND gate with inputs A and B is low when
a. A=B=0
b. A=B=1
c. A=0, B=1
d. both a and c
14: The output of an OR gate with inputs A and B is low when
a. A=B=0
b. A=B=1
c. A=0, B=1
d. Both a and c
15: A positive-going pulse is applied to an inverter. The time interval from the leading
edge of the input to the leading edge of the output is 7nsec. This parameter is
a. $\mathbf{t_{PHL}}$
b. $t_W$
c. $tPLH$
d. None
16: The AND operation can be produced with
a. Two NAND gates
b. Three NAND gates
c. Two NOR gates
d.One NOR gate
17: The OR operation can be produced with
a. Two NOR gates
b. Three NAND gates
c. Two OR gates
d. Both a and b
18: The expression of XOR gate is
a. $A\oplus B$
b. $A\bar{B}+\bar{A}B$
c.$\bar{A}B+\bar{A}B$
d. Both a and b
19: The expression of XNOR gate is
a. $(\bar{A}+B)(A+\bar{B})$
b. $\bar{A\ }\bar{B}+AB$
c. $A\bar{B}+\bar{A}B$
d. All
20: The universal gate(s) is/are
a. NAND
b. NOR
c. NOT
d. Both a and b
21: A variable is a symbol in a Boolean algebra used to represent
a. Data
b. A condition
c. An action
d. All of these
22: The domain of the expression ABCD ¯ + AB¯ + CD ¯ is
a. A and B
b. C and D
c. A, B, C and D
d. All of these
23: According to commutative law of multiplication
a. AB=BA
b. A=AA
c. (AB)C=A(BC)
d. A.0=A
24: Which of the following is not a valid rule of Boolean algebra
a. A+1=1
b. $\mathbf{A=\bar{A}}$
c. AA=A
d. A+0=A
25: A 3-bit parallel adder can add
a. Three 2-bit binary number
b. Two 3-bit binary number
c. Three bit at a time
d. Three bit in a sequence
26: Which of the following rules states that if one input of an AND gate is always 1, the
output is equal to the other input
a. A+1=1
b. A+A=A
c. A. A=A
d. A+1=A
27: An example of a sum-of-products expression is
a. $A+B(C+D)$
b. $\mathbf{\bar{A}B+A\bar{C}+A\bar{B}C}$
c. $(\bar{A}+B+C)(A+\bar{B}+C)$
d. Both a and b
28: An example of a standard SOP expression is
a. $\bar{A}B+A\bar{B}C$
b. A\bar{B}C+A\bar{C}D$$
c. $\mathbf{A\bar{B}+\bar{A}B}$
d. $A+BC$
29: An active-HIGH input S-R latch id formed by the cross coupling of
a. Two NOR gates
b. Two NAND gates
c. Two OR gates
d. Two AND gates
30: An active-LOW input S¯ – R¯ latch is formed by the cross coupling of
a. Two NOR gates
b. Two NAND gates
c. Two OR gates
d. Two AND gates
31: Which of the following is not true for an active LOW input S¯ – R¯ latch
a. $\bar{S}=\bar{R}=1,Q=no\ change,\bar{Q}=no\ change$
b. $\bar{S}=0,\bar{R}=1,\bar{Q}=1,\bar{Q}=0$
c. $\mathbf{\bar{S}=1,\bar{R}=0,Q=1,\bar{Q}=0}$
d. $\bar{S}=\bar{R}=0,Q=1,\bar{Q}=1$
32: For what combinations of the inputs D and EN will a D latch reset
a. $D=0,EN=0$
b. $D=0,EN=1$
c. $D=1,EN=0$
d. $D=1,EN=1$
33: A flip-flop changes its state during the . . . . . . clock pulse
a. Complete
b. Rising edge of
c. Falling edge of
d. Both b and c
34: A feature that distinguishes the J – K flip-flop from the D flip-flop is the
a. Toggle condition
b. Preset input
c. Clear input
d. Edge triggered
35: A flip-flop is SET when
a. $J=K=0$
b. J=K=1
c. J=1,K=0
d. J=0,K=1
36: A J – k flip-flop with J = K = 1 has a 10kHz clock input. The Q output is
a. Constantly HIGH
b. Constantly LOW
c. A square wave
d. A square wave
37: A one-shot is a type of . . . . . . multivibrator
a. Monostable
b. Astable
c. Bistable
d. None of these
38: The output pulse width of a one-shot depends on
a. Resistor
b. Capacitor
c. The supply voltage
d. Both a and b
39: A decade counter with a count of 0000 through 1001 is known as
a. ABCD counter
b. A binary counter
c. A decimal counter
d. None
40: A 3-bit binary counter has a maximum modulus of
a. 3
b. 6
c. 8
d. 16
41: A 5-bit binary counter has a maximum modulus of
a. 4
b. 8
c. 16
d. 32
42: A modulus-12 counter must have . . . . . . flip-flops
a. 12
b. 8
c. 4
d. 2
43: Which one of the following is an example of a counter with a truncated modulus
a. Modulus 8
b. Modulus 14
c. Modulus 4
d. Modulus 16
44: A BCD counter is an example of
a. A decade counter
b. A truncated-modulus counter
c. Both a and b
d. None
45: Which of the following is a valid state in an 8421 BCD counter
a. 1010
b. 1011
c. 1111
d. 1000
46: Three cascaded modulus-10 counters have an overall modulus of
a. 30
b. 100
c. 500
d. 1000
47: A 4-bit binary up/down counter is in the binary state of zero. The next state in the
DOWN mode is
a. 0001
b. 1111
c. 1000
d. 1110
48: The initial counter of a modulus-13 binary counter is
a. 0000
b. 1111
c. 1101
d. 1100
49: A CPLD is a
a. Controlled program logic device
b. Complex program logic device
c. Complex programmable logic device
d. Central programmable logic device
50: An FPGA is a
a. Field-programmable gate array
b. Fast-programmable gate array
c. Flash-programmable gate array
d. Flag-programmable gate array
51: A fixed-function IC package containing four AND gates is an example of
a. SSI
b. MSI
c. LSI
d. SMT
52: An MSI device has a circuit complexity of from . . . . . . equivalent gates on a chip
a. 10 to 100
b. 100 to 10000
c. 150 to 200
d. None
53: A fixed-function IC package containing 150 OR gates are an example of
a. MSI
b. SMT
c. SOIC
d. LSI
54: A VLSi device has a circuit complexity of from . . . . . . equivalent gate per chip
a. 0 to10
b. 10 to 100
c. More than 10000 to 100000
d. None
55: Most PLDs utilize an array of . . . . . . gate
a. NOT
b. NOR
c. OR
d. AND
56: The rows and columns of the interconnection matrix in an SPLD are connected using
a. Fuses
b. Switches
c. Gates
d. Transistors
57: An EPROM can be programmed using
a. Transistors
b. Diodes
c. Multiprogrammer
d. A device programmer
58: A macrocell is part of a
a. PAL
b. GAL
c. CPLD
d. All of these
59: When the frequency of the input signal to a CMOS gate is increased, the average power
dissipation
a. Decrease
b. Increase
c. Constant
d. None
60: CMOS operates more reliably than TTL in a high-noise environment because of its
a. Lower noise margin
b. Higher noise margin
c. Input capacitance
d. Smaller power
61: Proper handling of a CMOS device is necessary because of its
a. Low power
b. Construction
c. High-noise immunity
d. Susceptibility to electrostatic discharge
62: Which of the following is not a TTL circuit?
a. 74F00
b. 74AS00
c. 74HC00
d. 74LSS00
63: An LS TTL gate can derive a maximum of . . . . . . unit loads
a. 10
b. 20
c. 40
d. None
64: The main advantage of ECL over TTL or CMOS is
a. ECL is less expensive
b. ECL is faster
c. ECL consume less power
d. None
65: ECL cannot be used in
a. Heigh-noise environment
b. High frequency application
c. Low-noise environment
d. None
66: Power dissipation is smaller in
a. TTL
b. CMOS
c. ECL
d. None
67: Pull up resistor is connected to
a. Ground
b.
c.
d. None
68: An unconnected input on a TTL gate acts as a
a. Low
b. High
c. Ground
d. None
69: A register’s function include
a. Data storage
b. Data movement
c. Both a and b
d. None
70: To enter a byte of data serially into an 8-bit shift register, there must be
a. One clock pulse
b. Two clock pulses
c. Four clock pulses
d. Eight clock pulses
71: To parallel load a byte of date into a shift register with a synchronous load, there must
be
a. One clock pulse
b. Two clock pulses
c. Four clock pulses
d. Eight clock pulses
72: With a 100kHz clock frequency, eight bits can be serially entered into a shift register
in
a. $8\mu sec$
b. $\mathbf{ 80\mu sec}$
c.$8msec$
d. 80msec
73: A modulus-8 Johnson counter requires . . . . . . flip-flops
a. 2
b. 4
c. 8
d. 10
74: A modulus-8 ring counter requires . . . . . . flip-flops
a. 2
b. 4
c. 8
d. 10
75: When an 8-bit serial in/serial out shift register is used for a 24µsec time delay, the
clock frequency must be
a. 4MHz
b.3MHz
c. 333kHz
d.125kHz
76: Serial in/parallel out shift register IC is
a. 74HC164
b. 74HC165
c. 74HC64
d. None
77: Parallel in/serial out shift register IC is
a. 74HC164
b. 74HC165
c. 74HC64
d. 74HC65
78: Universal bidirectional shift register IC is
a. 74HC164
b. 74HC165
c. 74HC194
d.74HC195
79: Which of the following is not a type of ADC?
a. Flash ADC
b. Dual slope ADC
c. Sigma-delta ADC
d. Recessive Approximation ADC
80: An Op-Amp is a linear amplifier which has . . . . . . terminals
a. 2
b. 3
c. 5
d. 6
81: Generally, an analog signal can be reconstructed more accurately with
a. More quantization levels
b. Fewer quantization levels
c. ADC
d. DAC
82: A digital voltmeter uses a . . . . . . ADC
a. Flash
b. Sigma-delta
c. Dual-slope
d. None
83: The . . . . . . is an example of a successive-approximation ADC
a. ADC0804
b. ADC8004
c. ADC4008
d. ADC8040
84: DSPs are typically programmed in
a. The Fortran language
b. The C programming language
c. Both a and b
d. None
85: A digital signal processing system usually operates in
a. Real time
b. Imaginary time
c. Computer time
d. None
86: 2-bit binary-weighted input digital-to-analog converter requires . . . . . . resistors
a. 1
b. 2
c. 4
d. 8
87: Flash ADC provides a fast conversion time because of a high
a. Number of comparators
b. Throughput
c. Fanout
d. None
88: Which one is not the performance characteristics of a DAC
a. Resolution
b. Accuracy
c. Linearity
d. Digital signal processing
89: 1-to-16 DEMUX IC is
a. 74HC154
b. 74HC54
c. 74HC196
d. 74HC190
90: A dual four-input data selector IC is
a. 74HC154
b. 74HC151
c. 74HC153
d. 74HC152
91: An eight-input data selector IC is
a. 74HC151
b. 74HC152
c. 74HC153
d. 74HC154
92: A decimal-to-BCD priority encoder IC is
a. 74HC146
b. 74HC147
c. 74HC153
d. 74HC152
93: IC that decodes a BCD input and drives a 7-segment display is
a. 74HC146
b. 74HC147
c. 74HC46
d. 74HC47
94: The 1-of-16 decoder IC is
a. 74HC154
b. 74HC147
c. 74HC166
d. 74HC157
95: If a 1-of-16 decoder with active-low outputs exhibits a LOW on the decimal 12 output,
what are the inputs A3A2A1A0 =
a. 1010
b. 1110
c. 1100
d. 0100
96: A BCD-to-7-segment decoder has 0100 on its inputs. The active outputs are
a. a,c,f,g
b. b,c,f,g
c. b,c,e,f
d. b,d,e,g
97: If an octal-to-binary priority encoder has its 0,2,5, and 6 inputs at the active level, the
active HIGH binary output is
a. 110
b. 010
c. 101
d. 000
98: Data distributors are basically the same as
a. Decoders
b. Demultiplexers
c. Multiplexers
d. Encoders
99: Which of the following is a peripheral unit of a computer
a. Arithmetic and logic unit
b. Control unit
c. Memory unit
d. Keyboard
100: A 10-bit address bus support . . . . . . memory addresses
a. 100
b. 1000
c. 1024
d. 102
101: A bus that is used to transfer information both to and from the microprocessor is the
a. Address bus
b. Data bus
c. Both a and b
d. None
102: A system bus is composed of . . . . . . bus(es)
a. Address bus
b. Data bus
c. System bus
d. All
103: The bit capacity of a memory that has 512 addresses and can store 8 bits at each
address is
a. 512
b. 1024
c. 2048
d. 4096
104: A 16-bit word consists of
a. 3 bytes
b. 4 nibbles
c. 4 bytes
d. 3 bytes and 1 nibble
105: A ROM is a
a. Nonvolatile memory
b. Volatile memory
c. Read/write memory
d. Byte-organized memory
106: A memory with 512 addresses has
a. 512 address lines
b. 12 address lines
c. 1 address line
d. 9 address lines
